1. Field of the Invention
This invention relates to a circuit arrangement for providing input/output data coupling for bipolar transistor-compatible dynamic field-effect transistor memory circuits.
2. Description of the Prior Art
Large scale integrated memories including capacitors and field effect transistors are known in principle. U.S. Pat. No. 3,387,286 to Dennard describes a capacitive word-oriented memory whose memory cells consist of one field effect transistor and one capacitor each, one transistor connection being connected to the capacitor and the other to the bit line, the gate electrode being connected to the word line and the substrate to an operating voltage source.
Such a one-device cell has the advantage that it permits a high integration density with a relatively simple manufacturing process. The disadvantage of this memory cell, however, is that the writing-in and reading-out of the information is relatively slow.
The ever-increasing packing density of such memories, however, presents considerable problems in that the signal in the reading-out or sensing of the contents of a memory cell is so small that it is difficult to detect reliably. On the one hand this calls for extremely complicated sensing circuits, and on the other for precisely maintaining duration and levels of a control signal sequence. The signal sequence for a reading operation normally differs from that for a writing operation so that many auxiliary circuits are required in order to operate such a memory. Furthermore, the working speed decreases with an increasing size of the signal sensed.
In order to provide faster writing and reading cycles integrated dynamic semiconductor memories have been equipped with two-device cells. Such a memory with two independent storage capacitors, each accessible via one field effect transistor, has become known from IBM Technical Disclosure Bulletin, Vol. 18, No. 3, August 1975, pages 786 and 787, and from German Offenlegungeschrift No. 2,431,079. There, each memory cell is composed of two storage capacitors and two serially connected write/read field effect transistors. These series arrangements are provided between the two bit lines of a bit line pair and one common point of connection which is AC-connected to ground. A common word line joins the control electrodes of the two transistors. When the information of an addressed storage cell is read out, the differential signal on the bit line pair is applied to a latch for amplification.
This circuit arrangement permits a high writing and reading speed with a relatively simple control signal sequence.
For further improving the memory cycle time and for making the time control less complicated, U.S. Pat. No. 4,112,512 to Arzubi et al teaches a circuit which includes an early selection of the decoded bit line switches which are required for coupling memory cell array areas to data input/output lines, with a low level control pulse so that, as a function of the developing differential signal which is applied by a memory cell to the associated bit line pair and which is preferably pre-amplified, the switch-on threshold is exceeded for only one of the two bit line switches, whereas the bit line switch in the other bit line remains non-conductive and thus prevents a decrease of the potential of this bit line and of the cell node connected thereto.
Any further reduction of the access time by shortening the periods for sensing of the stored data is not possible without additional technical steps since, with shorter sensing time, the signal level of the information would no longer be reliably detectable.
Such circuit arrangements with dynamic one or two device cells have the further disadvantage that the sense latch for highly integrated TTL-compatible memory chips alone is not sufficient for the quick translation of the extremely small differential voltage into TTL signals, particularly when the data path to or from the memory cells shows a high capacity. This is particularly true when the parasitic capacity of the internal data bus to which the many bit lines are connected considerably reduces the writing and reading speed and furthermore affects a reliable detection and transfer of the information.
Another sensing arrangement known in the prior art is described in the IBM Technical Disclosure Bulletin, Vol. 17, No. 5, October 1974, pages 1361-2. There a pair of cross-coupled latches are provided which act in tandem to improve the performance of a memory access cycle. Such an arrangement is known to have been used in conjunction with a D.C. stable semiconductor memory cell as described in U.S. Pat. No. 3,949,385. In order to provide increased sensitivity to a stored information signal, a first preamplifier latch is set at approximately the same time as the bit switches are enabled, coupling a pair of bit lines within an array to a pair of common bit lines. The second latch is set shortly thereafter such that the preamplifier latch which has already amplified the information is used to provide a signal to set the second latch. A read output circuit is coupled to one of the common bit lines and is used to sense the signal on that common bit line in order to develop an output signal. Although not illustrated in the above two references, writing of data into the memory cells is accomplished, using the same timing signals, via a complementary driver circuit, responsive to a write signal, which enables the discharge of one of the common bit lines at a time prior to the setting of either latch and after the enabling of the bit switches. U.S. Pat. No. 4,125,878 to Watanabe teaches a somewhat similar arrangement in an array of one-device memory cells, however, the second sequential latch is effective only during a cycle in which information is read out of a memory cell but not during the writing of information. Additional subcombination arrangements have been disclosed for providing output signal driving circuits, such as found in U.S. Pat. No. 4,053,873 to Freeman et al, which teaches a push-pull driver circuit which is coupled to the output of a double rail sense amplifier by a pair of switches enabled by a memory enable clock signal such that data sensed on a particular memory cycle is available only at the end of each memory access cycle.